1. Technical Field of the Invention
The present invention relates to input/output devices and, in particular, to a programmable input/output controller for connecting a plurality of peripheral devices of different types to a host processing system. The present invention further relates to architectures for processing systems and, in particular, to an architecture facilitating context switched addressing, non-stacked machine operations and low latency interrupt handling.
2. Description of Related Art
It is of well known system design for a host processing system to be connected through an input/output controller to a peripheral device (comprising, for example, a printer or a disk drive). Conventionally, system designers have relied on the use of highly dedicated and functionally specific controllers for interfacing the host processing system with the included peripheral devices. These controllers comprise direct memory access (DMA.) controllers, small computer system interface (SCSI) controllers, multi-protocol serial communication controllers (SCCs) and disk controllers.
There are a number of known drawbacks to the continued use of such dedicated and specific input/output controllers in processing systems. First, because these controllers are typically standardized in design and manufactured for widespread commercial sale, it is difficult, if not impossible, to find a controller acceptable for use in a specialized application. Second, these controllers are designed to work only with a specific type of interface, and therefore cannot be used in conjunction with peripheral devices that do not support that specific interface type. Third, the trade-off for providing increased functionality in these controllers is typically a limitation on the number of channels available for connection to the peripheral devices. Other drawbacks of conventional controller design and operation are well known to those skilled in the art. Suffice it to say, however, that there is a need for a flexible/programmable controller capable of multiple channel operation in conjunction with a number of conventional and specialized peripheral devices and applications.
At the peripheral device level, data acquisition and transfer is bit or byte oriented and highly real time dependent, and thus controller designs tend to emphasize short response time and highly efficient operation. Conventional eight bit processor architectures implemented in input/output controllers, while possessing the advantages of programmability and flexibility of operation, simply are not capable of meeting the capacity and performance requirements of common controller design specifications. The current trend in processor architecture is then towards more and more powerful complex instruction set computing (CISC) designs having complicated addressing modes, large registers, larger address space and increased speed. However, CISC based processor systems provide unnecessary features not related to controller applications and are extraordinarily expensive rendering them unsuitable for use in input/output controllers. Another architecture providing programmability and flexibility of operation at a reasonable cost is accordingly needed for application to input/output controller design.